Silicon and germanium semiconductors have many uses. For example, virtually the entire microelectronics industry is based on silicon. In addition, due to a need for renewable sources of energy, cost effective methods for fabricating solar panels have become important. Silicon solar panels are usually fabricated from highly polished single-crystalline or polycrystalline round wafers sliced from single-crystalline or polycrystalline Si ingots. Sawing, polishing, and etching the wafers results in a costly (˜80%) loss, or “kerf,” of Si (or Ge) material. In addition, the process of growing single-crystalline or polycrystalline ingots is energy-intensive and costly. Furthermore, the size of the round wafers is limited, having a typical size of less than 200 mm or 300 mm in diameter. Therefore, many wafers are required to assemble one solar panel (or module)—a typical panel has dimensions of about 1.5 meters in length and about 1.0 meter in width. Furthermore, in order to minimize module efficiency losses due to unused area between round wafers, the round ingots are first machined into elongated semi-square rods prior to their being sliced to form semi-square wafers. This machining results in a further (˜20%) Si or Ge material loss. Alternatively, round wafers are packaged into the panels, thereby reducing the total panel conversion efficiency due to unutilized area between the round wafers which is not covered by solar cells. LCD display panels are fabricated from rectangular panels, but the silicon material is amorphous or, at best, small grain (<0.1 μm) (“microcrystalline”) Si material. In general, amorphous and/or small grain polycrystalline Si produces poor transistor performance, and low solar cell conversion efficiency. Single-crystalline, or large grain polycrystalline Si panels, offer superior solar cell conversion efficiency and/or LCD panel performance.
Other semiconductor wafer techniques do not require growing semiconductor ingots and then slicing the ingots into wafers. Conventional semiconductor foil or ribbon-edge growth methods, such as Edge-Defined Film Growth (“EFG”), Dendritic Web Ribbon Growth, Capillary Die Growth (of tubes), or Edge String Supports, involve growing a semiconductor ribbon or film from its melt, at a temperature slightly above its melting temperature (>1,414° C. for Si). In such ribbon-edge growth methods, the foil or ribbon grows from its edge, across a relatively small ribbon edge-liquid interfacial area, and along a direction parallel to the ribbon's length. The ribbon width is limited (only about 8 cm wide in string ribbon), and the growth rate along the length of the ribbon is only about 2-8 cm/min. As a result, ribbon-edge growth methods suffer low throughput of about 0.002 m2/min (20 cm2/min) for a string ribbon.
Furthermore, the molten source semiconductor material must be of high purity (or grade) and, therefore, is costly. As a result, conventional ribbon-edge growth methods require extensive energy usage due to the high operational temperature, high production costs, and low throughput.